In early MOS processing, a thick field oxide was grown over the entire surface of a semiconductor wafer. Areas were then opened in this thick layer for the transistor formation. This process had the problem of steep steps on the oxide which resulted in the breaking of metal lines deposited over these steps (step coverage). Modern MOS process techniques usually use the local oxidation of silicon process (LOCOS) which involves selective field oxidation of areas on the surface of a silicon substrate which will not be used for active devices. Selective oxidation has the advantage of resulting in a slope in the oxide step on the wafer surface, called a bird's beak, so that breaks are less likely to occur in the layers of interconnect material which run over these steps.
A bird's beak oxide slope occurs because thermal silicon dioxide grows fairly uniformly in all directions so lateral growth of oxide occurs under a polish stop layer such as silicon nitride (Si.sub.3 N.sub.4) in the form of a bird's beak. The bird's beak causes several undesirable effects. For example, in modern small geometry scaled processes, the bird's beak occupies needed area and can cause current leakage.
To avoid the problems associated with bird's beaks and field oxide films, isolation of individual devices can be done by etching shallow vertical `trenches` in the silicon between neighboring devices. Shallow trenches are principally used to control electron movement at a semiconductor surface, for example in MOSFET devices. Trench isolation allows devices to be moved much closer together and minimizes the problem of effective channel width control by eliminating the need for a field implant. Also, a more planar surface can be achieved by avoiding the formation of the bird's beak. A planar surface is beneficial for lithographic exposures since better resolution can be obtained without requiring additional depth of field to maintain a focussed image.
Conventional shallow trench isolation (STI) fabrication involves a series of steps including, silicon (Si) etching, oxide deposition and chemical mechanical polishing (CMP). To avoid erosion of oxide during CMP, a stopping layer is patterned on the oxide deposited in the shallow trench. A mask for patterning the stopping layer is needed which differs from the mask for Si etching.
FIGS. 1 (a)-1 (g) show a conventional method for fabricating an STI structure. On a silicon substrate layer 1, a resist pattern 2 for STI using a first mask is formed as shown in FIG. 1(a). Next, substrate 1 is etched (e.g., using reactive ion etching (RIE)) using resist pattern 2 as a mask to form a trench in the substrate 1 and the resist pattern 2 is removed. Then, a SiO.sub.2 layer 3 is deposited on the substrate 1 leaving the structure shown in FIG. 1(b). The SiO.sub.2 deposition can be performed by using thermal CVD (chemical vapor deposition) or plasma enhanced CVD (PECVD). These deposition methods result in the formation of areas 8 of SiO.sub.2 over the STI region enclosed by the dashed lines in FIG. 1(b). Thereafter, a silicon nitride (Si.sub.3 N.sub.4) (hereinafter referred to as SiN) layer 4 is deposited on the SiO.sub.2 layer 3 by CVD or PECVD resulting in the structure shown in FIG. 1(c). A resist pattern 5 is then formed using a second mask different from the first mask on a portion of the SiN layer 4 as shown in FIG. 1(d). The remaining portion of the SiN layer 4 is etched using resist pattern 5 as a mask and the resist pattern 5 is removed, leaving the structure shown in FIG. 1(e). The SiO.sub.2 layer 3 is polished using the SiN layer 4 as a polish stop layer resulting in the structure shown in FIG. 1(f). Next, the SiN layer 4 is removed using a well-known method such as RIE, chemical dry etching (CDE), or wet etching, leaving the shallow trench isolation structure of FIG. 1(g).
One of the problems which occurs with conventional methods of fabricating an STI structure such as the aforedescribed method is oxide erosion during CMP. The stopping layer is patterned on the oxide in the shallow trench as shown in FIGS. 1(d) and 1(e). Due to the areas 8 of SiO.sub.2, portions of the STI structure are not protected by the polish stop (SiN) layer 4. Consequently, during CMP, oxide erosion occurs at the unprotected portions of the STI structure which can produce a non-planar surface over the STI structure.
Moreover, the resist pattern 5 requires a mask different from the mask for forming the resist pattern 2 which is used for Si etching (FIG. 1(a)) because SiO.sub.2 deposition results in areas 8 of SiO.sub.2 covering portions of the width of the STI structure such that the gap g between the SiO.sub.2 sidewalls in the shallow trench is substantially less than the total width of the STI structure.
The oxide erosion tends to create high stress regions in adjacent device areas which car eventually result in the spontaneous formation of dislocations in the crystal lattice of the semiconductor substrate. Charge leakage from the devices formed in device areas of integrated circuits having STI structures has been associated with such dislocations.